Placement For Clock Period Minimization

A linear program is used to direct the placement of Standard Cells such that the clock period is minimized. Constraints upon the logic path delays and the clock signal arrival times at the flipflops allow multiple signals, corresponding to several clock cycles, to exist simultaneously on the logic signal paths during operation. The linear program constraints relate the clock period to the maximum and minimum logic path delays. Delays are achieved in the clock and logic paths by the use of delay elements and resistive polysilicon wires in the interconnection network. Categories: 3.1, placement, clock period minimization, linear programming